In most computer processor architectures, sequences of machine instructions are read sequentially from memory and executed directly by the hardware. There are some architectures and applications, however, where the instruction stream requires further processing before execution by the hardware. In one example, an instruction stream such as Java byte codes is not compatible with the underlying hardware. In this instance, the Java byte codes are translated to instructions that are executable by the underlying hardware. Other examples include code optimization and software-based identification and extraction of instruction-level parallelism. These types of processes are generally categorized as performing dynamic translation. Dynamic translation generally introduces significant overhead.
In a Java virtual machine (JVM) equipped with a just-in-time (JIT) compiler, sequences of Java byte codes that are frequently emulated with an interpreter running on the host processor are candidates for translation into native machine code. When a candidate is selected for translation, the sequence of Java byte codes is translated by the JIT compiler and stored in a translation cache. The next time the same byte code sequence is encountered, the JVM checks the translation cache for the presence of the translation of the byte codes in the translation cache. If the translation is present, in the general scenario the translation is executed instead of interpreting the byte code sequence. Because the native machine code will execute faster than interpreted byte codes, a Java application will gradually run faster as the translation cache is filled with translations of byte code sequences. The overhead involved in this type of arrangement is introduced by interpretation of byte code sequences, compilation of byte code sequences, and management of the translation cache. Other applications involving dynamic translation also introduce significant overhead.
Not only are the processing capacities of some processors stretched by the overhead associated with dynamic translation, but the same processors are deployed in arrangements that host other applications that require significant computational resources. For example, the same processor called upon to perform dynamic translation for one application may be called upon by other applications to perform data decompression, encryption, decryption and an assortment of other tasks. In mobile computing arrangements, the further requirement of minimal power consumption may further add to the challenges of developing an apparatus that meets the various design objectives.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.